From 70318492f3472ff2ec3b1735cf69a4eef1f6a51d Mon Sep 17 00:00:00 2001
From: Pacien TRAN-GIRARD
Date: Fri, 13 Jun 2014 16:06:19 +0200
Subject: Update project

---
 FPGA/display/lpm_shiftreg0.cmp | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 FPGA/display/lpm_shiftreg0.cmp

(limited to 'FPGA/display/lpm_shiftreg0.cmp')

diff --git a/FPGA/display/lpm_shiftreg0.cmp b/FPGA/display/lpm_shiftreg0.cmp
new file mode 100644
index 0000000..cc49c75
--- /dev/null
+++ b/FPGA/display/lpm_shiftreg0.cmp
@@ -0,0 +1,26 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_shiftreg0
+	PORT
+	(
+		aset		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
+		enable		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
+		shiftout		: OUT STD_LOGIC 
+	);
+end component;
-- 
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