From 70318492f3472ff2ec3b1735cf69a4eef1f6a51d Mon Sep 17 00:00:00 2001
From: Pacien TRAN-GIRARD
Date: Fri, 13 Jun 2014 16:06:19 +0200
Subject: Update project

---
 FPGA/pwm/greybox_tmp/cbx_args.txt        |   7 +
 FPGA/pwm/greybox_tmp/greybox_tmp/mgbt9.v |  52 ++++
 FPGA/pwm/greybox_tmp/greybox_tmp/mgtbb.v |  51 ++++
 FPGA/pwm/lpm_compare0.bsf                |  62 ++++
 FPGA/pwm/lpm_compare0.cmp                |  23 ++
 FPGA/pwm/lpm_compare0.qip                |   5 +
 FPGA/pwm/lpm_compare0.vhd                | 126 ++++++++
 FPGA/pwm/lpm_constant0.bsf               |  49 +++
 FPGA/pwm/lpm_constant0.cmp               |  21 ++
 FPGA/pwm/lpm_constant0.qip               |   5 +
 FPGA/pwm/lpm_constant0.vhd               | 109 +++++++
 FPGA/pwm/lpm_constant1.bsf               |  49 +++
 FPGA/pwm/lpm_constant1.cmp               |  21 ++
 FPGA/pwm/lpm_constant1.qip               |   5 +
 FPGA/pwm/lpm_constant1.vhd               | 109 +++++++
 FPGA/pwm/lpm_constant2.bsf               |  49 +++
 FPGA/pwm/lpm_constant2.cmp               |  21 ++
 FPGA/pwm/lpm_constant2.qip               |   5 +
 FPGA/pwm/lpm_constant2.vhd               | 109 +++++++
 FPGA/pwm/lpm_constant3.bsf               |  49 +++
 FPGA/pwm/lpm_constant3.cmp               |  21 ++
 FPGA/pwm/lpm_constant3.qip               |   5 +
 FPGA/pwm/lpm_constant3.vhd               | 109 +++++++
 FPGA/pwm/lpm_counter0.bsf                |  64 ++++
 FPGA/pwm/lpm_counter0.cmp                |  23 ++
 FPGA/pwm/lpm_counter0.qip                |   5 +
 FPGA/pwm/lpm_counter0.vhd                | 130 ++++++++
 FPGA/pwm/lpm_counter1.bsf                |  65 ++++
 FPGA/pwm/lpm_counter1.cmp                |  23 ++
 FPGA/pwm/lpm_counter1.qip                |   5 +
 FPGA/pwm/lpm_counter1.vhd                | 133 ++++++++
 FPGA/pwm/lpm_mux0.bsf                    |  82 +++++
 FPGA/pwm/lpm_mux0.cmp                    |  26 ++
 FPGA/pwm/lpm_mux0.qip                    |   5 +
 FPGA/pwm/lpm_mux0.vhd                    | 210 +++++++++++++
 FPGA/pwm/pwm.bdf                         | 502 +++++++++++++++++++++++++++++++
 FPGA/pwm/pwm.bsf                         |  64 ++++
 FPGA/pwm/pwm.qpf                         |  30 ++
 FPGA/pwm/pwm.qsf                         |  71 +++++
 FPGA/pwm/pwm.qws                         | Bin 0 -> 1406 bytes
 FPGA/pwm/pwm.tcl                         |   6 +
 41 files changed, 2506 insertions(+)
 create mode 100644 FPGA/pwm/greybox_tmp/cbx_args.txt
 create mode 100644 FPGA/pwm/greybox_tmp/greybox_tmp/mgbt9.v
 create mode 100644 FPGA/pwm/greybox_tmp/greybox_tmp/mgtbb.v
 create mode 100644 FPGA/pwm/lpm_compare0.bsf
 create mode 100644 FPGA/pwm/lpm_compare0.cmp
 create mode 100644 FPGA/pwm/lpm_compare0.qip
 create mode 100644 FPGA/pwm/lpm_compare0.vhd
 create mode 100644 FPGA/pwm/lpm_constant0.bsf
 create mode 100644 FPGA/pwm/lpm_constant0.cmp
 create mode 100644 FPGA/pwm/lpm_constant0.qip
 create mode 100644 FPGA/pwm/lpm_constant0.vhd
 create mode 100644 FPGA/pwm/lpm_constant1.bsf
 create mode 100644 FPGA/pwm/lpm_constant1.cmp
 create mode 100644 FPGA/pwm/lpm_constant1.qip
 create mode 100644 FPGA/pwm/lpm_constant1.vhd
 create mode 100644 FPGA/pwm/lpm_constant2.bsf
 create mode 100644 FPGA/pwm/lpm_constant2.cmp
 create mode 100644 FPGA/pwm/lpm_constant2.qip
 create mode 100644 FPGA/pwm/lpm_constant2.vhd
 create mode 100644 FPGA/pwm/lpm_constant3.bsf
 create mode 100644 FPGA/pwm/lpm_constant3.cmp
 create mode 100644 FPGA/pwm/lpm_constant3.qip
 create mode 100644 FPGA/pwm/lpm_constant3.vhd
 create mode 100644 FPGA/pwm/lpm_counter0.bsf
 create mode 100644 FPGA/pwm/lpm_counter0.cmp
 create mode 100644 FPGA/pwm/lpm_counter0.qip
 create mode 100644 FPGA/pwm/lpm_counter0.vhd
 create mode 100644 FPGA/pwm/lpm_counter1.bsf
 create mode 100644 FPGA/pwm/lpm_counter1.cmp
 create mode 100644 FPGA/pwm/lpm_counter1.qip
 create mode 100644 FPGA/pwm/lpm_counter1.vhd
 create mode 100644 FPGA/pwm/lpm_mux0.bsf
 create mode 100644 FPGA/pwm/lpm_mux0.cmp
 create mode 100644 FPGA/pwm/lpm_mux0.qip
 create mode 100644 FPGA/pwm/lpm_mux0.vhd
 create mode 100644 FPGA/pwm/pwm.bdf
 create mode 100644 FPGA/pwm/pwm.bsf
 create mode 100644 FPGA/pwm/pwm.qpf
 create mode 100644 FPGA/pwm/pwm.qsf
 create mode 100644 FPGA/pwm/pwm.qws
 create mode 100644 FPGA/pwm/pwm.tcl

(limited to 'FPGA/pwm')

diff --git a/FPGA/pwm/greybox_tmp/cbx_args.txt b/FPGA/pwm/greybox_tmp/cbx_args.txt
new file mode 100644
index 0000000..662f251
--- /dev/null
+++ b/FPGA/pwm/greybox_tmp/cbx_args.txt
@@ -0,0 +1,7 @@
+LPM_REPRESENTATION=UNSIGNED
+LPM_TYPE=LPM_COMPARE
+LPM_WIDTH=23
+DEVICE_FAMILY="Cyclone II"
+dataa
+datab
+alb
diff --git a/FPGA/pwm/greybox_tmp/greybox_tmp/mgbt9.v b/FPGA/pwm/greybox_tmp/greybox_tmp/mgbt9.v
new file mode 100644
index 0000000..90c1893
--- /dev/null
+++ b/FPGA/pwm/greybox_tmp/greybox_tmp/mgbt9.v
@@ -0,0 +1,52 @@
+//lpm_mux CBX_SINGLE_OUTPUT_FILE="ON" LPM_SIZE=4 LPM_TYPE="LPM_MUX" LPM_WIDTH=1 LPM_WIDTHS=2 data result sel
+//VERSION_BEGIN 13.0 cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratixii 2013:06:12:18:04:00:SJ cbx_util_mgl 2013:06:12:18:04:00:SJ  VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+
+// Copyright (C) 1991-2013 Altera Corporation
+//  Your use of Altera Corporation's design tools, logic functions 
+//  and other software and tools, and its AMPP partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Altera Program License 
+//  Subscription Agreement, Altera MegaCore Function License 
+//  Agreement, or other applicable license agreement, including, 
+//  without limitation, that your use is for the sole purpose of 
+//  programming logic devices manufactured by Altera and sold by 
+//  Altera or its authorized distributors.  Please refer to the 
+//  applicable agreement for further details.
+
+
+
+//synthesis_resources = lpm_mux 1 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  mgbt9
+	( 
+	data,
+	result,
+	sel) /* synthesis synthesis_clearbox=1 */;
+	input   [3:0]  data;
+	output   [0:0]  result;
+	input   [1:0]  sel;
+
+	wire  [0:0]   wire_mgl_prim1_result;
+
+	lpm_mux   mgl_prim1
+	( 
+	.data(data),
+	.result(wire_mgl_prim1_result),
+	.sel(sel));
+	defparam
+		mgl_prim1.lpm_size = 4,
+		mgl_prim1.lpm_type = "LPM_MUX",
+		mgl_prim1.lpm_width = 1,
+		mgl_prim1.lpm_widths = 2;
+	assign
+		result = wire_mgl_prim1_result;
+endmodule //mgbt9
+//VALID FILE
diff --git a/FPGA/pwm/greybox_tmp/greybox_tmp/mgtbb.v b/FPGA/pwm/greybox_tmp/greybox_tmp/mgtbb.v
new file mode 100644
index 0000000..8fab5c3
--- /dev/null
+++ b/FPGA/pwm/greybox_tmp/greybox_tmp/mgtbb.v
@@ -0,0 +1,51 @@
+//lpm_compare CBX_SINGLE_OUTPUT_FILE="ON" LPM_REPRESENTATION="UNSIGNED" LPM_TYPE="LPM_COMPARE" LPM_WIDTH=23 alb dataa datab
+//VERSION_BEGIN 13.0 cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratixii 2013:06:12:18:04:00:SJ cbx_util_mgl 2013:06:12:18:04:00:SJ  VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+
+// Copyright (C) 1991-2013 Altera Corporation
+//  Your use of Altera Corporation's design tools, logic functions 
+//  and other software and tools, and its AMPP partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Altera Program License 
+//  Subscription Agreement, Altera MegaCore Function License 
+//  Agreement, or other applicable license agreement, including, 
+//  without limitation, that your use is for the sole purpose of 
+//  programming logic devices manufactured by Altera and sold by 
+//  Altera or its authorized distributors.  Please refer to the 
+//  applicable agreement for further details.
+
+
+
+//synthesis_resources = lpm_compare 1 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  mgtbb
+	( 
+	alb,
+	dataa,
+	datab) /* synthesis synthesis_clearbox=1 */;
+	output   alb;
+	input   [22:0]  dataa;
+	input   [22:0]  datab;
+
+	wire  wire_mgl_prim1_alb;
+
+	lpm_compare   mgl_prim1
+	( 
+	.alb(wire_mgl_prim1_alb),
+	.dataa(dataa),
+	.datab(datab));
+	defparam
+		mgl_prim1.lpm_representation = "UNSIGNED",
+		mgl_prim1.lpm_type = "LPM_COMPARE",
+		mgl_prim1.lpm_width = 23;
+	assign
+		alb = wire_mgl_prim1_alb;
+endmodule //mgtbb
+//VALID FILE
diff --git a/FPGA/pwm/lpm_compare0.bsf b/FPGA/pwm/lpm_compare0.bsf
new file mode 100644
index 0000000..d31d901
--- /dev/null
+++ b/FPGA/pwm/lpm_compare0.bsf
@@ -0,0 +1,62 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 128 96)
+	(text "lpm_compare0" (rect 20 0 126 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 81 26 92)(font "Arial" ))
+	(port
+		(pt 0 48)
+		(input)
+		(text "dataa[22..0]" (rect 0 0 68 13)(font "Arial" (font_size 8)))
+		(text "dataa[22..0]" (rect 20 42 78 54)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "datab[22..0]" (rect 0 0 68 13)(font "Arial" (font_size 8)))
+		(text "datab[22..0]" (rect 20 58 78 70)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 128 56)
+		(output)
+		(text "aleb" (rect 0 0 25 13)(font "Arial" (font_size 8)))
+		(text "aleb" (rect 89 50 110 62)(font "Arial" (font_size 8)))
+		(line (pt 128 56)(pt 112 56))
+	)
+	(drawing
+		(text "unsigned compare" (rect 35 27 147 64)(font "Arial" ))
+		(line (pt 16 16)(pt 16 80))
+		(line (pt 16 16)(pt 112 16))
+		(line (pt 16 80)(pt 112 80))
+		(line (pt 112 16)(pt 112 80))
+		(line (pt 0 0)(pt 129 0))
+		(line (pt 129 0)(pt 129 98))
+		(line (pt 0 98)(pt 129 98))
+		(line (pt 0 0)(pt 0 98))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)
diff --git a/FPGA/pwm/lpm_compare0.cmp b/FPGA/pwm/lpm_compare0.cmp
new file mode 100644
index 0000000..2590a9e
--- /dev/null
+++ b/FPGA/pwm/lpm_compare0.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_compare0
+	PORT
+	(
+		dataa		: IN STD_LOGIC_VECTOR (22 DOWNTO 0);
+		datab		: IN STD_LOGIC_VECTOR (22 DOWNTO 0);
+		aleb		: OUT STD_LOGIC 
+	);
+end component;
diff --git a/FPGA/pwm/lpm_compare0.qip b/FPGA/pwm/lpm_compare0.qip
new file mode 100644
index 0000000..7632853
--- /dev/null
+++ b/FPGA/pwm/lpm_compare0.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_COMPARE"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_compare0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_compare0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_compare0.cmp"]
diff --git a/FPGA/pwm/lpm_compare0.vhd b/FPGA/pwm/lpm_compare0.vhd
new file mode 100644
index 0000000..cf52a6d
--- /dev/null
+++ b/FPGA/pwm/lpm_compare0.vhd
@@ -0,0 +1,126 @@
+-- megafunction wizard: %LPM_COMPARE%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: LPM_COMPARE 
+
+-- ============================================================
+-- File Name: lpm_compare0.vhd
+-- Megafunction Name(s):
+-- 			LPM_COMPARE
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_compare0 IS
+	PORT
+	(
+		dataa		: IN STD_LOGIC_VECTOR (22 DOWNTO 0);
+		datab		: IN STD_LOGIC_VECTOR (22 DOWNTO 0);
+		aleb		: OUT STD_LOGIC 
+	);
+END lpm_compare0;
+
+
+ARCHITECTURE SYN OF lpm_compare0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+
+
+
+	COMPONENT lpm_compare
+	GENERIC (
+		lpm_representation		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			aleb	: OUT STD_LOGIC ;
+			dataa	: IN STD_LOGIC_VECTOR (22 DOWNTO 0);
+			datab	: IN STD_LOGIC_VECTOR (22 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	aleb    <= sub_wire0;
+
+	LPM_COMPARE_component : LPM_COMPARE
+	GENERIC MAP (
+		lpm_representation => "UNSIGNED",
+		lpm_type => "LPM_COMPARE",
+		lpm_width => 23
+	)
+	PORT MAP (
+		dataa => dataa,
+		datab => datab,
+		aleb => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
+-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
+-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
+-- Retrieval info: PRIVATE: AleB NUMERIC "1"
+-- Retrieval info: PRIVATE: AltB NUMERIC "0"
+-- Retrieval info: PRIVATE: AneB NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
+-- Retrieval info: PRIVATE: Latency NUMERIC "0"
+-- Retrieval info: PRIVATE: PortBValue NUMERIC "0"
+-- Retrieval info: PRIVATE: Radix NUMERIC "10"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
+-- Retrieval info: PRIVATE: aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: clken NUMERIC "0"
+-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "23"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "23"
+-- Retrieval info: USED_PORT: aleb 0 0 0 0 OUTPUT NODEFVAL "aleb"
+-- Retrieval info: USED_PORT: dataa 0 0 23 0 INPUT NODEFVAL "dataa[22..0]"
+-- Retrieval info: USED_PORT: datab 0 0 23 0 INPUT NODEFVAL "datab[22..0]"
+-- Retrieval info: CONNECT: @dataa 0 0 23 0 dataa 0 0 23 0
+-- Retrieval info: CONNECT: @datab 0 0 23 0 datab 0 0 23 0
+-- Retrieval info: CONNECT: aleb 0 0 0 0 @aleb 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA/pwm/lpm_constant0.bsf b/FPGA/pwm/lpm_constant0.bsf
new file mode 100644
index 0000000..4e512d0
--- /dev/null
+++ b/FPGA/pwm/lpm_constant0.bsf
@@ -0,0 +1,49 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 112 48)
+	(text "lpm_constant0" (rect 14 0 117 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 33 26 44)(font "Arial" ))
+	(port
+		(pt 112 24)
+		(output)
+		(text "result[22..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
+		(text "0" (rect 87 18 94 30)(font "Arial" (font_size 8)))
+		(line (pt 112 24)(pt 96 24)(line_width 3))
+	)
+	(drawing
+		(text "23" (rect 94 27 199 64)(font "Arial" ))
+		(line (pt 106 20)(pt 98 28))
+		(line (pt 16 16)(pt 16 32))
+		(line (pt 16 16)(pt 96 16))
+		(line (pt 16 32)(pt 96 32))
+		(line (pt 96 16)(pt 96 32))
+		(line (pt 0 0)(pt 114 0))
+		(line (pt 114 0)(pt 114 50))
+		(line (pt 0 50)(pt 114 50))
+		(line (pt 0 0)(pt 0 50))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)
diff --git a/FPGA/pwm/lpm_constant0.cmp b/FPGA/pwm/lpm_constant0.cmp
new file mode 100644
index 0000000..2b6ed25
--- /dev/null
+++ b/FPGA/pwm/lpm_constant0.cmp
@@ -0,0 +1,21 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_constant0
+	PORT
+	(
+		result		: OUT STD_LOGIC_VECTOR (22 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA/pwm/lpm_constant0.qip b/FPGA/pwm/lpm_constant0.qip
new file mode 100644
index 0000000..ea26ffe
--- /dev/null
+++ b/FPGA/pwm/lpm_constant0.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.cmp"]
diff --git a/FPGA/pwm/lpm_constant0.vhd b/FPGA/pwm/lpm_constant0.vhd
new file mode 100644
index 0000000..57140dd
--- /dev/null
+++ b/FPGA/pwm/lpm_constant0.vhd
@@ -0,0 +1,109 @@
+-- megafunction wizard: %LPM_CONSTANT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: LPM_CONSTANT 
+
+-- ============================================================
+-- File Name: lpm_constant0.vhd
+-- Megafunction Name(s):
+-- 			LPM_CONSTANT
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_constant0 IS
+	PORT
+	(
+		result		: OUT STD_LOGIC_VECTOR (22 DOWNTO 0)
+	);
+END lpm_constant0;
+
+
+ARCHITECTURE SYN OF lpm_constant0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (22 DOWNTO 0);
+
+
+
+	COMPONENT lpm_constant
+	GENERIC (
+		lpm_cvalue		: NATURAL;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			result	: OUT STD_LOGIC_VECTOR (22 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	result    <= sub_wire0(22 DOWNTO 0);
+
+	LPM_CONSTANT_component : LPM_CONSTANT
+	GENERIC MAP (
+		lpm_cvalue => 0,
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "LPM_CONSTANT",
+		lpm_width => 23
+	)
+	PORT MAP (
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: Radix NUMERIC "10"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: Value NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "23"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "23"
+-- Retrieval info: USED_PORT: result 0 0 23 0 OUTPUT NODEFVAL "result[22..0]"
+-- Retrieval info: CONNECT: result 0 0 23 0 @result 0 0 23 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA/pwm/lpm_constant1.bsf b/FPGA/pwm/lpm_constant1.bsf
new file mode 100644
index 0000000..53cd0fc
--- /dev/null
+++ b/FPGA/pwm/lpm_constant1.bsf
@@ -0,0 +1,49 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 112 48)
+	(text "lpm_constant1" (rect 14 0 116 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 33 26 44)(font "Arial" ))
+	(port
+		(pt 112 24)
+		(output)
+		(text "result[22..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
+		(text "2500000" (rect 52 18 95 30)(font "Arial" (font_size 8)))
+		(line (pt 112 24)(pt 96 24)(line_width 3))
+	)
+	(drawing
+		(text "23" (rect 94 27 199 64)(font "Arial" ))
+		(line (pt 106 20)(pt 98 28))
+		(line (pt 16 16)(pt 16 32))
+		(line (pt 16 16)(pt 96 16))
+		(line (pt 16 32)(pt 96 32))
+		(line (pt 96 16)(pt 96 32))
+		(line (pt 0 0)(pt 114 0))
+		(line (pt 114 0)(pt 114 50))
+		(line (pt 0 50)(pt 114 50))
+		(line (pt 0 0)(pt 0 50))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)
diff --git a/FPGA/pwm/lpm_constant1.cmp b/FPGA/pwm/lpm_constant1.cmp
new file mode 100644
index 0000000..6e12b59
--- /dev/null
+++ b/FPGA/pwm/lpm_constant1.cmp
@@ -0,0 +1,21 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_constant1
+	PORT
+	(
+		result		: OUT STD_LOGIC_VECTOR (22 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA/pwm/lpm_constant1.qip b/FPGA/pwm/lpm_constant1.qip
new file mode 100644
index 0000000..497a35e
--- /dev/null
+++ b/FPGA/pwm/lpm_constant1.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.cmp"]
diff --git a/FPGA/pwm/lpm_constant1.vhd b/FPGA/pwm/lpm_constant1.vhd
new file mode 100644
index 0000000..c68518f
--- /dev/null
+++ b/FPGA/pwm/lpm_constant1.vhd
@@ -0,0 +1,109 @@
+-- megafunction wizard: %LPM_CONSTANT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: LPM_CONSTANT 
+
+-- ============================================================
+-- File Name: lpm_constant1.vhd
+-- Megafunction Name(s):
+-- 			LPM_CONSTANT
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_constant1 IS
+	PORT
+	(
+		result		: OUT STD_LOGIC_VECTOR (22 DOWNTO 0)
+	);
+END lpm_constant1;
+
+
+ARCHITECTURE SYN OF lpm_constant1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (22 DOWNTO 0);
+
+
+
+	COMPONENT lpm_constant
+	GENERIC (
+		lpm_cvalue		: NATURAL;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			result	: OUT STD_LOGIC_VECTOR (22 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	result    <= sub_wire0(22 DOWNTO 0);
+
+	LPM_CONSTANT_component : LPM_CONSTANT
+	GENERIC MAP (
+		lpm_cvalue => 2500000,
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "LPM_CONSTANT",
+		lpm_width => 23
+	)
+	PORT MAP (
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: Radix NUMERIC "10"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: Value NUMERIC "2500000"
+-- Retrieval info: PRIVATE: nBit NUMERIC "23"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "2500000"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "23"
+-- Retrieval info: USED_PORT: result 0 0 23 0 OUTPUT NODEFVAL "result[22..0]"
+-- Retrieval info: CONNECT: result 0 0 23 0 @result 0 0 23 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA/pwm/lpm_constant2.bsf b/FPGA/pwm/lpm_constant2.bsf
new file mode 100644
index 0000000..d02bfab
--- /dev/null
+++ b/FPGA/pwm/lpm_constant2.bsf
@@ -0,0 +1,49 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 112 48)
+	(text "lpm_constant2" (rect 14 0 117 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 33 26 44)(font "Arial" ))
+	(port
+		(pt 112 24)
+		(output)
+		(text "result[22..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
+		(text "3750000" (rect 52 18 95 30)(font "Arial" (font_size 8)))
+		(line (pt 112 24)(pt 96 24)(line_width 3))
+	)
+	(drawing
+		(text "23" (rect 94 27 199 64)(font "Arial" ))
+		(line (pt 106 20)(pt 98 28))
+		(line (pt 16 16)(pt 16 32))
+		(line (pt 16 16)(pt 96 16))
+		(line (pt 16 32)(pt 96 32))
+		(line (pt 96 16)(pt 96 32))
+		(line (pt 0 0)(pt 114 0))
+		(line (pt 114 0)(pt 114 50))
+		(line (pt 0 50)(pt 114 50))
+		(line (pt 0 0)(pt 0 50))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)
diff --git a/FPGA/pwm/lpm_constant2.cmp b/FPGA/pwm/lpm_constant2.cmp
new file mode 100644
index 0000000..e12bafa
--- /dev/null
+++ b/FPGA/pwm/lpm_constant2.cmp
@@ -0,0 +1,21 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_constant2
+	PORT
+	(
+		result		: OUT STD_LOGIC_VECTOR (22 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA/pwm/lpm_constant2.qip b/FPGA/pwm/lpm_constant2.qip
new file mode 100644
index 0000000..9ed83e8
--- /dev/null
+++ b/FPGA/pwm/lpm_constant2.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant2.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.cmp"]
diff --git a/FPGA/pwm/lpm_constant2.vhd b/FPGA/pwm/lpm_constant2.vhd
new file mode 100644
index 0000000..a1a52a1
--- /dev/null
+++ b/FPGA/pwm/lpm_constant2.vhd
@@ -0,0 +1,109 @@
+-- megafunction wizard: %LPM_CONSTANT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: LPM_CONSTANT 
+
+-- ============================================================
+-- File Name: lpm_constant2.vhd
+-- Megafunction Name(s):
+-- 			LPM_CONSTANT
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_constant2 IS
+	PORT
+	(
+		result		: OUT STD_LOGIC_VECTOR (22 DOWNTO 0)
+	);
+END lpm_constant2;
+
+
+ARCHITECTURE SYN OF lpm_constant2 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (22 DOWNTO 0);
+
+
+
+	COMPONENT lpm_constant
+	GENERIC (
+		lpm_cvalue		: NATURAL;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			result	: OUT STD_LOGIC_VECTOR (22 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	result    <= sub_wire0(22 DOWNTO 0);
+
+	LPM_CONSTANT_component : LPM_CONSTANT
+	GENERIC MAP (
+		lpm_cvalue => 3750000,
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "LPM_CONSTANT",
+		lpm_width => 23
+	)
+	PORT MAP (
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: Radix NUMERIC "10"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: Value NUMERIC "3750000"
+-- Retrieval info: PRIVATE: nBit NUMERIC "23"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "3750000"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "23"
+-- Retrieval info: USED_PORT: result 0 0 23 0 OUTPUT NODEFVAL "result[22..0]"
+-- Retrieval info: CONNECT: result 0 0 23 0 @result 0 0 23 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA/pwm/lpm_constant3.bsf b/FPGA/pwm/lpm_constant3.bsf
new file mode 100644
index 0000000..74aa934
--- /dev/null
+++ b/FPGA/pwm/lpm_constant3.bsf
@@ -0,0 +1,49 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 112 48)
+	(text "lpm_constant3" (rect 14 0 117 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 33 26 44)(font "Arial" ))
+	(port
+		(pt 112 24)
+		(output)
+		(text "result[22..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
+		(text "4500000" (rect 52 18 95 30)(font "Arial" (font_size 8)))
+		(line (pt 112 24)(pt 96 24)(line_width 3))
+	)
+	(drawing
+		(text "23" (rect 94 27 199 64)(font "Arial" ))
+		(line (pt 106 20)(pt 98 28))
+		(line (pt 16 16)(pt 16 32))
+		(line (pt 16 16)(pt 96 16))
+		(line (pt 16 32)(pt 96 32))
+		(line (pt 96 16)(pt 96 32))
+		(line (pt 0 0)(pt 114 0))
+		(line (pt 114 0)(pt 114 50))
+		(line (pt 0 50)(pt 114 50))
+		(line (pt 0 0)(pt 0 50))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)
diff --git a/FPGA/pwm/lpm_constant3.cmp b/FPGA/pwm/lpm_constant3.cmp
new file mode 100644
index 0000000..173566d
--- /dev/null
+++ b/FPGA/pwm/lpm_constant3.cmp
@@ -0,0 +1,21 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_constant3
+	PORT
+	(
+		result		: OUT STD_LOGIC_VECTOR (22 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA/pwm/lpm_constant3.qip b/FPGA/pwm/lpm_constant3.qip
new file mode 100644
index 0000000..c50d3e0
--- /dev/null
+++ b/FPGA/pwm/lpm_constant3.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant3.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.cmp"]
diff --git a/FPGA/pwm/lpm_constant3.vhd b/FPGA/pwm/lpm_constant3.vhd
new file mode 100644
index 0000000..bdc3792
--- /dev/null
+++ b/FPGA/pwm/lpm_constant3.vhd
@@ -0,0 +1,109 @@
+-- megafunction wizard: %LPM_CONSTANT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: LPM_CONSTANT 
+
+-- ============================================================
+-- File Name: lpm_constant3.vhd
+-- Megafunction Name(s):
+-- 			LPM_CONSTANT
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_constant3 IS
+	PORT
+	(
+		result		: OUT STD_LOGIC_VECTOR (22 DOWNTO 0)
+	);
+END lpm_constant3;
+
+
+ARCHITECTURE SYN OF lpm_constant3 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (22 DOWNTO 0);
+
+
+
+	COMPONENT lpm_constant
+	GENERIC (
+		lpm_cvalue		: NATURAL;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			result	: OUT STD_LOGIC_VECTOR (22 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	result    <= sub_wire0(22 DOWNTO 0);
+
+	LPM_CONSTANT_component : LPM_CONSTANT
+	GENERIC MAP (
+		lpm_cvalue => 4500000,
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "LPM_CONSTANT",
+		lpm_width => 23
+	)
+	PORT MAP (
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: Radix NUMERIC "10"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: Value NUMERIC "4500000"
+-- Retrieval info: PRIVATE: nBit NUMERIC "23"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "4500000"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "23"
+-- Retrieval info: USED_PORT: result 0 0 23 0 OUTPUT NODEFVAL "result[22..0]"
+-- Retrieval info: CONNECT: result 0 0 23 0 @result 0 0 23 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA/pwm/lpm_counter0.bsf b/FPGA/pwm/lpm_counter0.bsf
new file mode 100644
index 0000000..5cc02c4
--- /dev/null
+++ b/FPGA/pwm/lpm_counter0.bsf
@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 144 96)
+	(text "lpm_counter0" (rect 33 0 129 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 81 26 92)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 51 38)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 80 96)
+		(input)
+		(text "aclr" (rect 0 0 13 22)(font "Arial" (font_size 8))(vertical))
+		(text "aclr" (rect 74 57 86 75)(font "Arial" (font_size 8))(vertical))
+		(line (pt 80 96)(pt 80 80))
+	)
+	(port
+		(pt 144 40)
+		(output)
+		(text "q[18..0]" (rect 0 0 43 13)(font "Arial" (font_size 8)))
+		(text "q[18..0]" (rect 89 34 126 46)(font "Arial" (font_size 8)))
+		(line (pt 144 40)(pt 128 40)(line_width 3))
+	)
+	(drawing
+		(text "up counter" (rect 84 23 214 56)(font "Arial" ))
+		(line (pt 16 16)(pt 16 80))
+		(line (pt 16 16)(pt 128 16))
+		(line (pt 16 80)(pt 128 80))
+		(line (pt 128 16)(pt 128 80))
+		(line (pt 0 0)(pt 146 0))
+		(line (pt 146 0)(pt 146 98))
+		(line (pt 0 98)(pt 146 98))
+		(line (pt 0 0)(pt 0 98))
+		(line (pt 16 26)(pt 22 32))
+		(line (pt 22 32)(pt 16 38))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)
diff --git a/FPGA/pwm/lpm_counter0.cmp b/FPGA/pwm/lpm_counter0.cmp
new file mode 100644
index 0000000..f505116
--- /dev/null
+++ b/FPGA/pwm/lpm_counter0.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_counter0
+	PORT
+	(
+		aclr		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (18 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA/pwm/lpm_counter0.qip b/FPGA/pwm/lpm_counter0.qip
new file mode 100644
index 0000000..f7b47d7
--- /dev/null
+++ b/FPGA/pwm/lpm_counter0.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_COUNTER"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_counter0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter0.cmp"]
diff --git a/FPGA/pwm/lpm_counter0.vhd b/FPGA/pwm/lpm_counter0.vhd
new file mode 100644
index 0000000..9a8bd70
--- /dev/null
+++ b/FPGA/pwm/lpm_counter0.vhd
@@ -0,0 +1,130 @@
+-- megafunction wizard: %LPM_COUNTER%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: LPM_COUNTER 
+
+-- ============================================================
+-- File Name: lpm_counter0.vhd
+-- Megafunction Name(s):
+-- 			LPM_COUNTER
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_counter0 IS
+	PORT
+	(
+		aclr		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (18 DOWNTO 0)
+	);
+END lpm_counter0;
+
+
+ARCHITECTURE SYN OF lpm_counter0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (18 DOWNTO 0);
+
+
+
+	COMPONENT lpm_counter
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_port_updown		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			aclr	: IN STD_LOGIC ;
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (18 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(18 DOWNTO 0);
+
+	LPM_COUNTER_component : LPM_COUNTER
+	GENERIC MAP (
+		lpm_direction => "UP",
+		lpm_port_updown => "PORT_UNUSED",
+		lpm_type => "LPM_COUNTER",
+		lpm_width => 19
+	)
+	PORT MAP (
+		aclr => aclr,
+		clock => clock,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
+-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
+-- Retrieval info: PRIVATE: Direction NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
+-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "19"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
+-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "19"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+-- Retrieval info: USED_PORT: q 0 0 19 0 OUTPUT NODEFVAL "q[18..0]"
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 19 0 @q 0 0 19 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA/pwm/lpm_counter1.bsf b/FPGA/pwm/lpm_counter1.bsf
new file mode 100644
index 0000000..385ae09
--- /dev/null
+++ b/FPGA/pwm/lpm_counter1.bsf
@@ -0,0 +1,65 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_counter1" (rect 33 0 128 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 65 26 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 51 38)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 80 80)
+		(input)
+		(text "aclr" (rect 0 0 13 22)(font "Arial" (font_size 8))(vertical))
+		(text "aclr" (rect 74 41 86 59)(font "Arial" (font_size 8))(vertical))
+		(line (pt 80 80)(pt 80 64))
+	)
+	(port
+		(pt 144 40)
+		(output)
+		(text "q[22..0]" (rect 0 0 43 13)(font "Arial" (font_size 8)))
+		(text "q[22..0]" (rect 89 34 126 46)(font "Arial" (font_size 8)))
+		(line (pt 144 40)(pt 128 40)(line_width 3))
+	)
+	(drawing
+		(text "modulus 5000000" (rect 54 31 182 72)(font "Arial" ))
+		(text "up counter" (rect 84 23 214 56)(font "Arial" ))
+		(line (pt 16 16)(pt 16 64))
+		(line (pt 16 16)(pt 128 16))
+		(line (pt 16 64)(pt 128 64))
+		(line (pt 128 16)(pt 128 64))
+		(line (pt 0 0)(pt 146 0))
+		(line (pt 146 0)(pt 146 82))
+		(line (pt 0 82)(pt 146 82))
+		(line (pt 0 0)(pt 0 82))
+		(line (pt 16 26)(pt 22 32))
+		(line (pt 22 32)(pt 16 38))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)
diff --git a/FPGA/pwm/lpm_counter1.cmp b/FPGA/pwm/lpm_counter1.cmp
new file mode 100644
index 0000000..7954133
--- /dev/null
+++ b/FPGA/pwm/lpm_counter1.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_counter1
+	PORT
+	(
+		aclr		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (22 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA/pwm/lpm_counter1.qip b/FPGA/pwm/lpm_counter1.qip
new file mode 100644
index 0000000..2bfe235
--- /dev/null
+++ b/FPGA/pwm/lpm_counter1.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_COUNTER"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_counter1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter1.cmp"]
diff --git a/FPGA/pwm/lpm_counter1.vhd b/FPGA/pwm/lpm_counter1.vhd
new file mode 100644
index 0000000..3d48255
--- /dev/null
+++ b/FPGA/pwm/lpm_counter1.vhd
@@ -0,0 +1,133 @@
+-- megafunction wizard: %LPM_COUNTER%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: LPM_COUNTER 
+
+-- ============================================================
+-- File Name: lpm_counter1.vhd
+-- Megafunction Name(s):
+-- 			LPM_COUNTER
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_counter1 IS
+	PORT
+	(
+		aclr		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (22 DOWNTO 0)
+	);
+END lpm_counter1;
+
+
+ARCHITECTURE SYN OF lpm_counter1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (22 DOWNTO 0);
+
+
+
+	COMPONENT lpm_counter
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_modulus		: NATURAL;
+		lpm_port_updown		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			aclr	: IN STD_LOGIC ;
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (22 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(22 DOWNTO 0);
+
+	LPM_COUNTER_component : LPM_COUNTER
+	GENERIC MAP (
+		lpm_direction => "UP",
+		lpm_modulus => 5000000,
+		lpm_port_updown => "PORT_UNUSED",
+		lpm_type => "LPM_COUNTER",
+		lpm_width => 23
+	)
+	PORT MAP (
+		aclr => aclr,
+		clock => clock,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
+-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
+-- Retrieval info: PRIVATE: Direction NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
+-- Retrieval info: PRIVATE: ModulusValue NUMERIC "5000000"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "23"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
+-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "5000000"
+-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "23"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+-- Retrieval info: USED_PORT: q 0 0 23 0 OUTPUT NODEFVAL "q[22..0]"
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 23 0 @q 0 0 23 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA/pwm/lpm_mux0.bsf b/FPGA/pwm/lpm_mux0.bsf
new file mode 100644
index 0000000..3f80c05
--- /dev/null
+++ b/FPGA/pwm/lpm_mux0.bsf
@@ -0,0 +1,82 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design to