From 70318492f3472ff2ec3b1735cf69a4eef1f6a51d Mon Sep 17 00:00:00 2001
From: Pacien TRAN-GIRARD
Date: Fri, 13 Jun 2014 16:06:19 +0200
Subject: Update project

---
 FPGA/top/LCD_controller.bsf       |  141 ++++++
 FPGA/top/clock_divider.bsf        |   61 +++
 FPGA/top/codec_clock.bsf          |   50 ++
 FPGA/top/codec_clock.qsf          |   78 +++
 FPGA/top/codec_config.bsf         |   75 +++
 FPGA/top/codec_dac.bsf            |  113 +++++
 FPGA/top/dds_sinus.bsf            |   68 +++
 FPGA/top/display.bsf              |   83 ++-
 FPGA/top/greybox_tmp/cbx_args.txt |    9 +
 FPGA/top/lcd_message.bsf          |   85 ++++
 FPGA/top/lpm_compare0.bsf         |   62 +++
 FPGA/top/lpm_counter0.bsf         |   64 +++
 FPGA/top/lpm_counter1.bsf         |   65 +++
 FPGA/top/lpm_counter1.qip         |    0
 FPGA/top/lpm_mux0.bsf             |   82 +++
 FPGA/top/message.bsf              |   43 ++
 FPGA/top/pwm.bsf                  |   64 +++
 FPGA/top/sound_gene.bsf           |  113 +++++
 FPGA/top/top.bdf                  | 1015 +++++++++++++++++++++++++++++++++----
 FPGA/top/top.bsf                  |  232 +++++++++
 FPGA/top/top.qsf                  |   57 ++-
 FPGA/top/top.tcl                  |  212 ++++++++
 FPGA/top/useless.bsf              |   71 +++
 23 files changed, 2711 insertions(+), 132 deletions(-)
 create mode 100644 FPGA/top/LCD_controller.bsf
 create mode 100644 FPGA/top/clock_divider.bsf
 create mode 100644 FPGA/top/codec_clock.bsf
 create mode 100644 FPGA/top/codec_clock.qsf
 create mode 100644 FPGA/top/codec_config.bsf
 create mode 100644 FPGA/top/codec_dac.bsf
 create mode 100644 FPGA/top/dds_sinus.bsf
 create mode 100644 FPGA/top/greybox_tmp/cbx_args.txt
 create mode 100644 FPGA/top/lcd_message.bsf
 create mode 100644 FPGA/top/lpm_compare0.bsf
 create mode 100644 FPGA/top/lpm_counter0.bsf
 create mode 100644 FPGA/top/lpm_counter1.bsf
 create mode 100644 FPGA/top/lpm_counter1.qip
 create mode 100644 FPGA/top/lpm_mux0.bsf
 create mode 100644 FPGA/top/message.bsf
 create mode 100644 FPGA/top/pwm.bsf
 create mode 100644 FPGA/top/sound_gene.bsf
 create mode 100644 FPGA/top/top.bsf
 create mode 100644 FPGA/top/top.tcl
 create mode 100644 FPGA/top/useless.bsf

(limited to 'FPGA/top')

diff --git a/FPGA/top/LCD_controller.bsf b/FPGA/top/LCD_controller.bsf
new file mode 100644
index 0000000..9f6a194
--- /dev/null
+++ b/FPGA/top/LCD_controller.bsf
@@ -0,0 +1,141 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 232 256)
+	(text "LCD_controller" (rect 5 0 66 12)(font "Arial" ))
+	(text "inst" (rect 8 224 20 236)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 27 31 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "resetn" (rect 0 0 24 12)(font "Arial" ))
+		(text "resetn" (rect 21 43 45 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "en_250kHz" (rect 0 0 44 12)(font "Arial" ))
+		(text "en_250kHz" (rect 21 59 65 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "mode[1..0]" (rect 0 0 41 12)(font "Arial" ))
+		(text "mode[1..0]" (rect 21 75 62 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "char[7..0]" (rect 0 0 37 12)(font "Arial" ))
+		(text "char[7..0]" (rect 21 91 58 103)(font "Arial" ))
+		(line (pt 0 96)(pt 16 96)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "address[6..0]" (rect 0 0 51 12)(font "Arial" ))
+		(text "address[6..0]" (rect 21 107 72 119)(font "Arial" ))
+		(line (pt 0 112)(pt 16 112)(line_width 3))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "write_char" (rect 0 0 41 12)(font "Arial" ))
+		(text "write_char" (rect 21 123 62 135)(font "Arial" ))
+		(line (pt 0 128)(pt 16 128)(line_width 1))
+	)
+	(port
+		(pt 0 144)
+		(input)
+		(text "write_address" (rect 0 0 55 12)(font "Arial" ))
+		(text "write_address" (rect 21 139 76 151)(font "Arial" ))
+		(line (pt 0 144)(pt 16 144)(line_width 1))
+	)
+	(port
+		(pt 0 160)
+		(input)
+		(text "D" (rect 0 0 7 12)(font "Arial" ))
+		(text "D" (rect 21 155 28 167)(font "Arial" ))
+		(line (pt 0 160)(pt 16 160)(line_width 1))
+	)
+	(port
+		(pt 0 176)
+		(input)
+		(text "C" (rect 0 0 7 12)(font "Arial" ))
+		(text "C" (rect 21 171 28 183)(font "Arial" ))
+		(line (pt 0 176)(pt 16 176)(line_width 1))
+	)
+	(port
+		(pt 0 192)
+		(input)
+		(text "B" (rect 0 0 5 12)(font "Arial" ))
+		(text "B" (rect 21 187 26 199)(font "Arial" ))
+		(line (pt 0 192)(pt 16 192)(line_width 1))
+	)
+	(port
+		(pt 216 32)
+		(output)
+		(text "ready" (rect 0 0 23 12)(font "Arial" ))
+		(text "ready" (rect 172 27 195 39)(font "Arial" ))
+		(line (pt 216 32)(pt 200 32)(line_width 1))
+	)
+	(port
+		(pt 216 64)
+		(output)
+		(text "LCD_RS" (rect 0 0 40 12)(font "Arial" ))
+		(text "LCD_RS" (rect 155 59 195 71)(font "Arial" ))
+		(line (pt 216 64)(pt 200 64)(line_width 1))
+	)
+	(port
+		(pt 216 80)
+		(output)
+		(text "LCD_RW" (rect 0 0 44 12)(font "Arial" ))
+		(text "LCD_RW" (rect 151 75 195 87)(font "Arial" ))
+		(line (pt 216 80)(pt 200 80)(line_width 1))
+	)
+	(port
+		(pt 216 96)
+		(output)
+		(text "LCD_EN" (rect 0 0 40 12)(font "Arial" ))
+		(text "LCD_EN" (rect 155 91 195 103)(font "Arial" ))
+		(line (pt 216 96)(pt 200 96)(line_width 1))
+	)
+	(port
+		(pt 216 48)
+		(bidir)
+		(text "LCD_data[7..0]" (rect 0 0 62 12)(font "Arial" ))
+		(text "LCD_data[7..0]" (rect 133 43 195 55)(font "Arial" ))
+		(line (pt 216 48)(pt 200 48)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 200 224)(line_width 1))
+	)
+)
diff --git a/FPGA/top/clock_divider.bsf b/FPGA/top/clock_divider.bsf
new file mode 100644
index 0000000..de8cb37
--- /dev/null
+++ b/FPGA/top/clock_divider.bsf
@@ -0,0 +1,61 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 176 96)
+	(text "clock_divider" (rect 5 0 56 12)(font "Arial" ))
+	(text "inst" (rect 8 64 20 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 27 31 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "resetn" (rect 0 0 24 12)(font "Arial" ))
+		(text "resetn" (rect 21 43 45 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 160 32)
+		(output)
+		(text "en_user" (rect 0 0 33 12)(font "Arial" ))
+		(text "en_user" (rect 106 27 139 39)(font "Arial" ))
+		(line (pt 160 32)(pt 144 32)(line_width 1))
+	)
+	(parameter
+		"board_frequency"
+		"50000000.0"
+		""
+		(type "PARAMETER_SIGNED_FLOAT")	)
+	(parameter
+		"user_frequency"
+		"4.0"
+		""
+		(type "PARAMETER_SIGNED_FLOAT")	)
+	(drawing
+		(rectangle (rect 16 16 144 64)(line_width 1))
+	)
+	(annotation_block (parameter)(rect 176 -64 276 16))
+)
diff --git a/FPGA/top/codec_clock.bsf b/FPGA/top/codec_clock.bsf
new file mode 100644
index 0000000..c112470
--- /dev/null
+++ b/FPGA/top/codec_clock.bsf
@@ -0,0 +1,50 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 16 16 152 112)
+	(text "codec_clock" (rect 5 0 76 13)(font "Arial" (font_size 8)))
+	(text "inst" (rect 8 81 26 92)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 18 13)(font "Arial" (font_size 8)))
+		(text "clk" (rect 21 27 39 40)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "resetn" (rect 0 0 36 13)(font "Arial" (font_size 8)))
+		(text "resetn" (rect 21 43 57 56)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 136 32)
+		(output)
+		(text "xti_mclk" (rect 0 0 48 13)(font "Arial" (font_size 8)))
+		(text "xti_mclk" (rect 67 27 115 40)(font "Arial" (font_size 8)))
+		(line (pt 136 32)(pt 120 32))
+	)
+	(drawing
+		(rectangle (rect 16 16 120 80))
+	)
+)
diff --git a/FPGA/top/codec_clock.qsf b/FPGA/top/codec_clock.qsf
new file mode 100644
index 0000000..c11cd5a
--- /dev/null
+++ b/FPGA/top/codec_clock.qsf
@@ -0,0 +1,78 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 15:18:56  mai 26, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		codec_clock_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name DEVICE EP2C35F672C6
+set_global_assignment -name TOP_LEVEL_ENTITY codec_clock
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:18:56  MAI 26, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+set_global_assignment -name VHDL_FILE ../vhdl/clock_divider.vhd
+set_global_assignment -name BDF_FILE codec_clock.bdf
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_location_assignment PIN_N25 -to alarm_user
+set_location_assignment PIN_P25 -to speed_user[0]
+set_location_assignment PIN_AE14 -to speed_user[1]
+set_location_assignment PIN_N26 -to fan_auto_user
+set_location_assignment PIN_AE23 -to alarm
+set_location_assignment PIN_AF23 -to fan_auto
+set_location_assignment PIN_AB21 -to speed[0]
+set_location_assignment PIN_AC22 -to speed[1]
+set_location_assignment PIN_N2 -to clk
+set_location_assignment PIN_G26 -to resetn
+set_location_assignment PIN_M23 -to hot
+set_location_assignment PIN_K26 -to fan
+set_location_assignment PIN_B4 -to aud_bclk
+set_location_assignment PIN_A4 -to aud_dacdat
+set_location_assignment PIN_C6 -to aud_daclrck
+set_location_assignment PIN_A5 -to aud_xck
+set_location_assignment PIN_A6 -to i2c_sclk
+set_location_assignment PIN_B6 -to i2c_sdat
+set_location_assignment PIN_M20 -to sound_high_level
+set_location_assignment PIN_Y18 -to led_fan
+set_location_assignment PIN_AE22 -to end_config
+set_location_assignment PIN_M25 -to xti_mclk
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/FPGA/top/codec_config.bsf b/FPGA/top/codec_config.bsf
new file mode 100644
index 0000000..b2b4d9f
--- /dev/null
+++ b/FPGA/top/codec_config.bsf
@@ -0,0 +1,75 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 184 128)
+	(text "codec_config" (rect 5 0 58 12)(font "Arial" ))
+	(text "inst" (rect 8 96 20 108)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 27 31 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "resetn" (rect 0 0 24 12)(font "Arial" ))
+		(text "resetn" (rect 21 43 45 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 168 32)
+		(output)
+		(text "end_config" (rect 0 0 43 12)(font "Arial" ))
+		(text "end_config" (rect 104 27 147 39)(font "Arial" ))
+		(line (pt 168 32)(pt 152 32)(line_width 1))
+	)
+	(port
+		(pt 168 48)
+		(output)
+		(text "i2c_scl" (rect 0 0 27 12)(font "Arial" ))
+		(text "i2c_scl" (rect 120 43 147 55)(font "Arial" ))
+		(line (pt 168 48)(pt 152 48)(line_width 1))
+	)
+	(port
+		(pt 168 64)
+		(bidir)
+		(text "i2c_sda" (rect 0 0 30 12)(font "Arial" ))
+		(text "i2c_sda" (rect 117 59 147 71)(font "Arial" ))
+		(line (pt 168 64)(pt 152 64)(line_width 1))
+	)
+	(parameter
+		"system_frequency"
+		"50000000.0"
+		""
+		(type "PARAMETER_SIGNED_FLOAT")	)
+	(parameter
+		"i2c_rate"
+		"20000.0"
+		""
+		(type "PARAMETER_SIGNED_FLOAT")	)
+	(drawing
+		(rectangle (rect 16 16 152 96)(line_width 1))
+	)
+	(annotation_block (parameter)(rect 184 -64 284 16))
+)
diff --git a/FPGA/top/codec_dac.bsf b/FPGA/top/codec_dac.bsf
new file mode 100644
index 0000000..695e7d0
--- /dev/null
+++ b/FPGA/top/codec_dac.bsf
@@ -0,0 +1,113 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 272 160)
+	(text "codec_dac" (rect 5 0 48 12)(font "Arial" ))
+	(text "inst" (rect 8 128 20 140)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 27 31 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "resetn" (rect 0 0 24 12)(font "Arial" ))
+		(text "resetn" (rect 21 43 45 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "go" (rect 0 0 9 12)(font "Arial" ))
+		(text "go" (rect 21 59 30 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "data_in[data_width-1..0]" (rect 0 0 90 12)(font "Arial" ))
+		(text "data_in[data_width-1..0]" (rect 21 75 111 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 256 32)
+		(output)
+		(text "tempo_dac" (rect 0 0 44 12)(font "Arial" ))
+		(text "tempo_dac" (rect 191 27 235 39)(font "Arial" ))
+		(line (pt 256 32)(pt 240 32)(line_width 1))
+	)
+	(port
+		(pt 256 48)
+		(output)
+		(text "end_dac" (rect 0 0 34 12)(font "Arial" ))
+		(text "end_dac" (rect 201 43 235 55)(font "Arial" ))
+		(line (pt 256 48)(pt 240 48)(line_width 1))
+	)
+	(port
+		(pt 256 64)
+		(output)
+		(text "codec_dac_bclk" (rect 0 0 64 12)(font "Arial" ))
+		(text "codec_dac_bclk" (rect 171 59 235 71)(font "Arial" ))
+		(line (pt 256 64)(pt 240 64)(line_width 1))
+	)
+	(port
+		(pt 256 80)
+		(output)
+		(text "codec_dac_data" (rect 0 0 66 12)(font "Arial" ))
+		(text "codec_dac_data" (rect 169 75 235 87)(font "Arial" ))
+		(line (pt 256 80)(pt 240 80)(line_width 1))
+	)
+	(port
+		(pt 256 96)
+		(output)
+		(text "codec_dac_lrck" (rect 0 0 63 12)(font "Arial" ))
+		(text "codec_dac_lrck" (rect 172 91 235 103)(font "Arial" ))
+		(line (pt 256 96)(pt 240 96)(line_width 1))
+	)
+	(parameter
+		"system_frequency"
+		"50000000.0"
+		""
+		(type "PARAMETER_SIGNED_FLOAT")	)
+	(parameter
+		"sample_rate"
+		"48000.0"
+		""
+		(type "PARAMETER_SIGNED_FLOAT")	)
+	(parameter
+		"data_width"
+		"16"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(parameter
+		"channel_num"
+		"2"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(drawing
+		(rectangle (rect 16 16 240 128)(line_width 1))
+	)
+	(annotation_block (parameter)(rect 272 -64 372 16))
+)
diff --git a/FPGA/top/dds_sinus.bsf b/FPGA/top/dds_sinus.bsf
new file mode 100644
index 0000000..97636d4
--- /dev/null
+++ b/FPGA/top/dds_sinus.bsf
@@ -0,0 +1,68 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 224 128)
+	(text "dds_sinus" (rect 5 0 45 12)(font "Arial" ))
+	(text "inst" (rect 8 96 20 108)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "resetn" (rect 0 0 24 12)(font "Arial" ))
+		(text "resetn" (rect 21 27 45 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 43 31 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "en" (rect 0 0 9 12)(font "Arial" ))
+		(text "en" (rect 21 59 30 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 208 32)
+		(output)
+		(text "dds_out[n_data-1..0]" (rect 0 0 80 12)(font "Arial" ))
+		(text "dds_out[n_data-1..0]" (rect 107 27 187 39)(font "Arial" ))
+		(line (pt 208 32)(pt 192 32)(line_width 3))
+	)
+	(parameter
+		"N_data"
+		"16"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(parameter
+		"M"
+		"12"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(drawing
+		(rectangle (rect 16 16 192 96)(line_width 1))
+	)
+	(annotation_block (parameter)(rect 224 -64 324 16))
+)
diff --git a/FPGA/top/display.bsf b/FPGA/top/display.bsf
index ed4adb7..829f8f9 100644
--- a/FPGA/top/display.bsf
+++ b/FPGA/top/display.bsf
@@ -20,52 +20,101 @@ applicable agreement for further details.
 */
 (header "symbol" (version "1.2"))
 (symbol
-	(rect 16 16 192 112)
-	(text "display" (rect 5 0 46 13)(font "Arial" (font_size 8)))
-	(text "inst" (rect 8 81 25 92)(font "Arial" ))
+	(rect 16 16 192 208)
+	(text "display" (rect 5 0 47 13)(font "Arial" (font_size 8)))
+	(text "inst" (rect 8 177 26 188)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "fan_auto" (rect 0 0 49 13)(font "Arial" (font_size 8)))
-		(text "fan_auto" (rect 21 27 70 40)(font "Arial" (font_size 8)))
+		(text "clk" (rect 0 0 18 13)(font "Arial" (font_size 8)))
+		(text "clk" (rect 21 27 39 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "alarm_user" (rect 0 0 63 13)(font "Arial" (font_size 8)))
-		(text "alarm_user" (rect 21 43 84 56)(font "Arial" (font_size 8)))
+		(text "resetn" (rect 0 0 36 13)(font "Arial" (font_size 8)))
+		(text "resetn" (rect 21 43 57 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48))
 	)
 	(port
 		(pt 0 64)
 		(input)
-		(text "speed[1..0]" (rect 0 0 62 13)(font "Arial" (font_size 8)))
-		(text "speed[1..0]" (rect 21 59 83 72)(font "Arial" (font_size 8)))
-		(line (pt 0 64)(pt 16 64)(line_width 3))
+		(text "fan_auto" (rect 0 0 50 13)(font "Arial" (font_size 8)))
+		(text "fan_auto" (rect 21 59 71 72)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 16 64))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "alarm_user" (rect 0 0 64 13)(font "Arial" (font_size 8)))
+		(text "alarm_user" (rect 21 75 85 88)(font "Arial" (font_size 8)))
+		(line (pt 0 80)(pt 16 80))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "speed[1..0]" (rect 0 0 63 13)(font "Arial" (font_size 8)))
+		(text "speed[1..0]" (rect 21 91 84 104)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 16 96)(line_width 3))
 	)
 	(port
 		(pt 176 32)
 		(output)
-		(text "hex7[6..0]" (rect 0 0 55 13)(font "Arial" (font_size 8)))
-		(text "hex7[6..0]" (rect 100 27 155 40)(font "Arial" (font_size 8)))
+		(text "hex7[6..0]" (rect 0 0 56 13)(font "Arial" (font_size 8)))
+		(text "hex7[6..0]" (rect 99 27 155 40)(font "Arial" (font_size 8)))
 		(line (pt 176 32)(pt 160 32)(line_width 3))
 	)
 	(port
 		(pt 176 48)
 		(output)
-		(text "hex6[6..0]" (rect 0 0 55 13)(font "Arial" (font_size 8)))
-		(text "hex6[6..0]" (rect 100 43 155 56)(font "Arial" (font_size 8)))
+		(text "hex6[6..0]" (rect 0 0 56 13)(font "Arial" (font_size 8)))
+		(text "hex6[6..0]" (rect 99 43 155 56)(font "Arial" (font_size 8)))
 		(line (pt 176 48)(pt 160 48)(line_width 3))
 	)
 	(port
 		(pt 176 64)
 		(output)
-		(text "hex4[6..0]" (rect 0 0 55 13)(font "Arial" (font_size 8)))
-		(text "hex4[6..0]" (rect 100 59 155 72)(font "Arial" (font_size 8)))
+		(text "hex5[6..0]" (rect 0 0 56 13)(font "Arial" (font_size 8)))
+		(text "hex5[6..0]" (rect 99 59 155 72)(font "Arial" (font_size 8)))
 		(line (pt 176 64)(pt 160 64)(line_width 3))
 	)
+	(port
+		(pt 176 80)
+		(output)
+		(text "hex4[6..0]" (rect 0 0 56 13)(font "Arial" (font_size 8)))
+		(text "hex4[6..0]" (rect 99 75 155 88)(font "Arial" (font_size 8)))
+		(line (pt 176 80)(pt 160 80)(line_width 3))
+	)
+	(port
+		(pt 176 96)
+		(output)
+		(text "hex3[6..0]" (rect 0 0 56 13)(font "Arial" (font_size 8)))
+		(text "hex3[6..0]" (rect 99 91 155 104)(font "Arial" (font_size 8)))
+		(line (pt 176 96)(pt 160 96)(line_width 3))
+	)
+	(port
+		(pt 176 112)
+		(output)
+		(text "hex2[6..0]" (rect 0 0 56 13)(font "Arial" (font_size 8)))
+		(text "hex2[6..0]" (rect 99 107 155 120)(font "Arial" (font_size 8)))
+		(line (pt 176 112)(pt 160 112)(line_width 3))
+	)
+	(port
+		(pt 176 128)
+		(output)
+		(text "hex1[6..0]" (rect 0 0 56 13)(font "Arial" (font_size 8)))
+		(text "hex1[6..0]" (rect 99 123 155 136)(font "Arial" (font_size 8)))
+		(line (pt 176 128)(pt 160 128)(line_width 3))
+	)
+	(port
+		(pt 176 144)
+		(output)
+		(text "hex0[6..0]" (rect 0 0 56 13)(font "Arial" (font_size 8)))
+		(text "hex0[6..0]" (rect 99 139 155 152)(font "Arial" (font_size 8)))
+		(line (pt 176 144)(pt 160 144)(line_width 3))
+	)
 	(drawing
-		(rectangle (rect 16 16 160 80))
+		(rectangle (rect 16 16 160 176))
 	)
 )
diff --git a/FPGA/top/greybox_tmp/cbx_args.txt b/FPGA/top/greybox_tmp/cbx_args.txt
new file mode 100644
index 0000000..cd08835
--- /dev/null
+++ b/FPGA/top/greybox_tmp/cbx_args.txt
@@ -0,0 +1,9 @@
+LPM_DIRECTION=UP
+LPM_MODULUS=5000000
+LPM_PORT_UPDOWN=PORT_UNUSED
+LPM_TYPE=LPM_COUNTER
+LPM_WIDTH=23
+DEVICE_FAMILY="Cyclone II"
+aclr
+clock
+q
diff --git a/FPGA/top/lcd_message.bsf b/FPGA/top/lcd_message.bsf
new file mode 100644
index 0000000..946183f
--- /dev/null
+++ b/FPGA/top/lcd_message.bsf
@@ -0,0 +1,85 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 216 160)
+	(text "lcd_message" (rect 5 0 58 12)(font "Arial" ))
+	(text "inst" (rect 8 128 20 140)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 27 31 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "resetn" (rect 0 0 24 12)(font "Arial" ))
+		(text "resetn" (rect 21 43 45 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 200 48)
+		(output)
+		(text "LCD_ON" (rect 0 0 40 12)(font "Arial" ))
+		(text "LCD_ON" (rect 139 43 179 55)(font "Arial" ))
+		(line (pt 200 48)(pt 184 48)(line_width 1))
+	)
+	(port
+		(pt 200 64)
+		(output)
+		(text "LCD_BLON" (rect 0 0 51 12)(font "Arial" ))
+		(text "LCD_BLON" (rect 128 59 179 71)(font "Arial" ))
+		(line (pt 200 64)(pt 184 64)(line_width 1))
+	)
+	(port
+		(pt 200 80)
+		(output)
+		(text "LCD_RS" (rect 0 0 40 12)(font "Arial" ))
+		(text "LCD_RS" (rect 139 75 179 87)(font "Arial" ))
+		(line (pt 200 80)(pt 184 80)(line_width 1))
+	)
+	(port
+		(pt 200 96)
+		(output)
+		(text "LCD_RW" (rect 0 0 44 12)(font "Arial" ))
+		(text "LCD_RW" (rect 135 91 179 103)(font "Arial" ))
+		(line (pt 200 96)(pt 184 96)(line_width 1))
+	)
+	(port
+		(pt 200 112)
+		(output)
+		(text "LCD_EN" (rect 0 0 40 12)(font "Arial" ))
+		(text "LCD_EN" (rect 139 107 179 119)(font "Arial" ))
+		(line (pt 200 112)(pt 184 112)(line_width 1))
+	)
+	(port
+		(pt 200 32)
+		(bidir)
+		(text "LCD_DATA[7..0]" (rect 0 0 75 12)(font "Arial" ))
+		(text "LCD_DATA[7..0]" (rect 104 27 179 39)(font "Arial" ))
+		(line (pt 200 32)(pt 184 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 184 128)(line_width 1))
+	)
+)
diff --git a/FPGA/top/lpm_compare0.bsf b/FPGA/top/lpm_compare0.bsf
new file mode 100644
index 0000000..d31d901
--- /dev/null
+++ b/FPGA/top/lpm_compare0.bsf
@@ -0,0 +1,62 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 128 96)
+	(text "lpm_compare0" (rect 20 0 126 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 81 26 92)(font "Arial" ))
+	(port
+		(pt 0 48)
+		(input)
+		(text "dataa[22..0]" (rect 0 0 68 13)(font "Arial" (font_size 8)))
+		(text "dataa[22..0]" (rect 20 42 78 54)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "datab[22..0]" (rect 0 0 68 13)(font "Arial" (font_size 8)))
+		(text "datab[22..0]" (rect 20 58 78 70)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 128 56)
+		(output)
+		(text "aleb" (rect 0 0 25 13)(font "Arial" (font_size 8)))
+		(text "aleb" (rect 89 50 110 62)(font "Arial" (font_size 8)))
+		(line (pt 128 56)(pt 112 56))
+	)
+	(drawing
+		(text "unsigned compare" (rect 35 27 147 64)(font "Arial" ))
+		(line (pt 16 16)(pt 16 80))
+		(line (pt 16 16)(pt 112 16))
+		(line (pt 16 80)(pt 112 80))
+		(line (pt 112 16)(pt 112 80))
+		(line (pt 0 0)(pt 129 0))
+		(line (pt 129 0)(pt 129 98))
+		(line (pt 0 98)(pt 129 98))
+		(line (pt 0 0)(pt 0 98))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)
diff --git a/FPGA/top/lpm_counter0.bsf b/FPGA/top/lpm_counter0.bsf
new file mode 100644
index 0000000..5cc02c4
--- /dev/null
+++ b/FPGA/top/lpm_counter0.bsf
@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 144 96)
+	(text "lpm_counter0" (rect 33 0 129 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 81 26 92)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 51 38)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 80 96)
+		(input)
+		(text "aclr" (rect 0 0 13 22)(font "Arial" (font_size 8))(vertical))
+		(text "aclr" (rect 74 57 86 75)(font "Arial" (font_size 8))(vertical))
+		(line (pt 80 96)(pt 80 80))
+	)
+	(port
+		(pt 144 40)
+		(output)
+		(text "q[18..0]" (rect 0 0 43 13)(font "Arial" (font_size 8)))
+		(text "q[18..0]" (rect 89 34 126 46)(font "Arial" (font_size 8)))
+		(line (pt 144 40)(pt 128 40)(line_width 3))
+	)
+	(drawing
+		(text "up counter" (rect 84 23 214 56)(font "Arial" ))
+		(line (pt 16 16)(pt 16 80))
+		(line (pt 16 16)(pt 128 16))
+		(line (pt 16 80)(pt 128 80))
+		(line (pt 128 16)(pt 128 80))
+		(line (pt 0 0)(pt 146 0))
+		(line (pt 146 0)(pt 146 98))
+		(line (pt 0 98)(pt 146 98))
+		(line (pt 0 0)(pt 0 98))
+		(line (pt 16 26)(pt 22 32))
+		(line (pt 22 32)(pt 16 38))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)
diff --git a/FPGA/top/lpm_counter1.bsf b/FPGA/top/lpm_counter1.bsf
new file mode 100644
index 0000000..385ae09
--- /dev/null
+++ b/FPGA/top/lpm_counter1.bsf
@@ -0,0 +1,65 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_counter1" (rect 33 0 128 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 65 26 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 51 38)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 80 80)
+		(input)
+		(text "aclr" (rect 0 0 13 22)(font "Arial" (font_size 8))(vertical))
+		(text "aclr" (rect 74 41 86 59)(font "Arial" (font_size 8))(vertical))
+		(line (pt 80 80)(pt 80 64))
+	)
+	(port
+		(pt 144 40)
+		(output)
+		(text "q[22..0]" (rect 0 0 43 13)(font "Arial" (font_size 8)))
+		(text "q[22..0]" (rect 89 34 126 46)(font "Arial" (font_size 8)))
+		(line (pt 144 40)(pt 128 40)(line_width 3))
+	)
+	(drawing
+		(text "modulus 5000000" (rect 54 31 182 72)(font "Arial" ))
+		(text "up counter" (rect 84 23 214 56)(font "Arial" ))
+		(line (pt 16 16)(pt 16 64))
+		(line (pt 16 16)(pt 128 16))
+		(line (pt 16 64)(pt 128 64))
+		(line (pt 128 16)(pt 128 64))
+		(line (pt 0 0)(pt 146 0))
+		(line (pt 146 0)(pt 146 82))
+		(line (pt 0 82)(pt 146 82))
+		(line (pt 0 0)(pt 0 82))
+		(line (pt 16 26)(pt 22 32))
+		(line (pt 22 32)(pt 16 38))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)
diff --git a/FPGA/top/lpm_counter1.qip b/FPGA/top/lpm_counter1.qip
new file mode 100644
index 0000000..e69de29
diff --git a/FPGA/top/lpm_mux0.bsf b/FPGA/top/lpm_mux0.bsf
new file mode 100644
index 0000000..3f80c05
--- /dev/null
+++ b/FPGA/top/lpm_mux0.bsf
@@ -0,0 +1,82 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 144 112)
+	(text "lpm_mux0" (rect 43 0 117 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 97 26 108)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data3x[22..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data3x[22..0]" (rect 4 27 67 39)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 64 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data2x[22..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data2x[22..0]" (rect 4 43 67 55)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 64 56)(line_width 3))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "data1x[22..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data1x[22..0]" (rect 4 59 67 71)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 64 72)(line_width 3))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "data0x[22..0]" (rect 0 0 74 13)(font "Arial" (font_size 8)))
+		(text "data0x[22..0]" (rect 4 75 67 87)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 64 88)(line_width 3))
+	)
+	(port
+		(pt 72 112)
+		(input)
+		(text "sel[1..0]" (rect 0 0 13 46)(font "Arial" (font_size 8))(vertical))
+		(text "sel[1..0]" (rect 66 57 78 95)(font "Arial" (font_size 8))(vertical))
+		(line (pt 72 112)(pt 72 100)(line_width 3))
+	)
+	(port
+		(pt 144 64)
+		(output)
+		(text "result[22..0]" (rect 0 0 67 13)(font "Arial" (font_size 8)))
+		(text "result[22..0]" (rect 85 51 142 63)(font "Arial" (font_size 8)))
+		(line (pt 144 64)(pt 80 64)(line_width 3))
+	)
+	(drawing
+		(line (pt 64 24)(pt 64 104))
+		(line (pt 64 24)(pt 80 32))
+		(line (pt 64 104)(pt 80 96))
+		(line (pt 80 32)(pt 80 96))
+		(line (pt 0 0)(pt 146 0))
+		(line (pt 146 0)(pt 146 114))
+		(line (pt 0 114)(pt 146 114))
+		(line (pt 0 0)(pt 0 114))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)
diff --git a/FPGA/top/message.bsf b/FPGA/top/message.bsf
new file mode 100644
index 0000000..9e08aba
--- /dev/null
+++ b/FPGA/top/message.bsf
@@ -0,0 +1,43 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 184 96)
+	(text "message" (rect 5 0 41 12)(font "Arial" ))
+	(text "inst" (rect 8 64 20 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "adr[4..0]" (rect 0 0 34 12)(font "Arial" ))
+		(text "adr[4..0]" (rect 21 27 55 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 168 32)
+		(output)
+		(text "do[7..0]" (rect 0 0 29 12)(font "Arial" ))
+		(text "do[7..0]" (rect 118 27 147 39)(font "Arial" ))
+		(line (pt 168 32)(pt 152 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 152 64)(line_width 1))
+	)
+)
diff --git a/FPGA/top/pwm.bsf b/FPGA/top/pwm.bsf
new file mode 100644
index 0000000..010307a
--- /dev/null
+++ b/FPGA/top/pwm.bsf
@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 16 16 176 112)
+	(text "pwm" (rect 5 0 33 13)(font "Arial" (font_size 8)))
+	(text "inst" (rect 8 81 26 92)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 18 13)(font "Arial" (font_size 8)))
+		(text "clk" (rect 21 27 39 40)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "resetn" (rect 0 0 36 13)(font "Arial" (font_size 8)))
+		(text "resetn" (rect 21 43 57 56)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "speed[1..0]" (rect 0 0 63 13)(font "Arial" (font_size 8)))
+		(text "speed[1..0]" (rect 21 59 84 72)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 160 32)
+		(output)
+		(text "fan" (rect 0 0 18 13)(font "Arial" (font_size 8)))
+		(text "fan" (rect 121 27 139 40)(font "Arial" (font_size 8)))
+		(line (pt 160 32)(pt 144 32))
+	)
+	(port
+		(pt 160 48)
+		(output)
+		(text "led_fan" (rect 0 0 42 13)(font "Arial" (font_size 8)))
+		(text "led_fan" (rect 97 43 139 56)(font "Arial" (font_size 8)))
+		(line (pt 160 48)(pt 144 48))
+	)
+	(drawing
+		(rectangle (rect 16 16 144 80))
+	)
+)
diff --git a/FPGA/top/sound_gene.bsf b/FPGA/top/sound_gene.bsf
new file mode 100644
index 0000000..d2af6c5
--- /dev/null
+++ b/FPGA/top/sound_gene.bsf
@@ -0,0 +1,113 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 16 16 176 208)
+	(text "sound_gene" (rect 5 0 75 13)(font "Arial" (font_size 8)))
+	(text "inst" (rect 8 177 26 188)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 18 13)(font "Arial" (font_size 8)))
+		(text "clk" (rect 21 27 39 40)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "resetn" (rect 0 0 36 13)(font "Arial" (font_size 8)))
+		(text "resetn" (rect 21 43 57 56)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "alarm" (rect 0 0 33 13)(font "Arial" (font_size 8)))
+		(text "alarm" (rect 21 59 54 72)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 16 64))
+	)
+	(port
+		(pt 160 32)
+		(output)
+		(text "end_config" (rect 0 0 63 13)(font "Arial" (font_size 8)))
+		(text "end_config" (rect 76 27 139 40)(font "Arial" (font_size 8)))
+		(line (pt 160 32)(pt 144 32))
+	)
+	(port
+		(pt 160 64)
+		(output)
+		(text "i2c_sclk" (rect 0 0 47 13)(font "Arial" (font_size 8)))
+		(text "i2c_sclk" (rect 92 59 139 72)(font "Arial" (font_size 8)))
+		(line (pt 160 64)(pt 144 64))
+	)
+	(port
+		(pt 160 80)
+		(output)
+		(text "aud_bclk" (rect 0 0 53 13)(font "Arial" (font_size 8)))
+		(text "aud_bclk" (rect 86 75 139 88)(font "Arial" (font_size 8)))
+		(line (pt 160 80)(pt 144 80))
+	)
+	(port
+		(pt 160 96)
+		(output)
+		(text "aud_dacdat" (rect 0 0 67 13)(font "Arial" (font_size 8)))
+		(text "aud_dacdat" (rect 72 91 139 104)(font "Arial" (font_size 8)))
+		(line (pt 160 96)(pt 144 96))
+	)
+	(port
+		(pt 160 112)
+		(output)
+		(text "aud_daclrck" (rect 0 0 70 13)(font "Arial" (font_size 8)))
+		(text "aud_daclrck" (rect 69 107 139 120)(font "Arial" (font_size 8)))
+		(line (pt 160 112)(pt 144 112))
+	)
+	(port
+		(pt 160 128)
+		(output)
+		(text "aud_xck" (rect 0 0 49 13)(font "Arial" (font_size 8)))
+		(text "aud_xck" (rect 90 123 139 136)(font "Arial" (font_size 8)))
+		(line (pt 160 128)(pt 144 128))
+	)
+	(port
+		(pt 160 144)
+		(output)
+		(text "xti_mclk" (rect 0 0 48 13)(font "Arial" (font_size 8)))
+		(text "xti_mclk" (rect 91 139 139 152)(font "Arial" (font_size 8)))
+		(line (pt 160 144)(pt 144 144))
+	)
+	(port
+		(pt 160 160)
+		(output)
+		(text "end_tempo" (rect 0 0 64 13)(font "Arial" (font_size 8)))
+		(text "end_tempo" (rect 75 155 139 168)(font "Arial" (font_size 8)))
+		(line (pt 160 160)(pt 144 160))
+	)
+	(port
+		(pt 160 48)
+		(bidir)
+		(text "i2c_sdat" (rect 0 0 48 13)(font "Arial" (font_size 8)))
+		(text "i2c_sdat" (rect 91 43 139 56)(font "Arial" (font_size 8)))
+		(line (pt 160 48)(pt 144 48))
+	)
+	(drawing
+		(rectangle (rect 16 16 144 176))
+	)
+)
diff --git a/FPGA/top/top.bdf b/FPGA/top/top.bdf
index 7fd8d63..57674c9 100644
--- a/FPGA/top/top.bdf
+++ b/FPGA/top/top.bdf
@@ -22,7 +22,7 @@ applicable agreement for further details.
 (pin
 	(input)
 	(rect 48 120 216 136)
-	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
 	(text "clk" (rect 5 0 20 11)(font "Arial" ))
 	(pt 168 8)
 	(drawing
@@ -33,12 +33,13 @@ applicable agreement for further details.
 		(line (pt 109 4)(pt 113 8))
 		(line (pt 109 12)(pt 113 8))
 	)
-	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -8 136 48 152))
 )
 (pin
 	(input)
 	(rect 48 136 216 152)
-	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
 	(text "resetn" (rect 5 0 36 11)(font "Arial" ))
 	(pt 168 8)
 	(drawing
@@ -49,13 +50,14 @@ applicable agreement for further details.
 		(line (pt 109 4)(pt 113 8))
 		(line (pt 109 12)(pt 113 8))
 	)
-	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -16 152 48 168))
 )
 (pin
 	(input)
 	(rect 40 152 216 168)
-	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
-	(text "speed_user[1..0]" (rect 5 0 88 11)(font "Arial" ))
+	(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
+	(text "speed_user[1..0]" (rect 5 0 87 11)(font "Arial" ))
 	(pt 176 8)
 	(drawing
 		(line (pt 92 12)(pt 117 12))
@@ -65,13 +67,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8))
 		(line (pt 117 12)(pt 121 8))
 	)
-	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -32 168 40 184))
 )
 (pin
 	(input)
 	(rect 48 168 216 184)
-	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
-	(text "fan_auto_user" (rect 5 0 77 11)(font "Arial" ))
+	(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
+	(text "fan_auto_user" (rect 5 0 78 11)(font "Arial" ))
 	(pt 168 8)
 	(drawing
 		(line (pt 84 12)(pt 109 12))
@@ -81,12 +84,13 @@ applicable agreement for further details.
 		(line (pt 109 4)(pt 113 8))
 		(line (pt 109 12)(pt 113 8))
 	)
-	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -16 184 48 200))
 )
 (pin
 	(input)
 	(rect 48 184 216 200)
-	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
 	(text "alarm_user" (rect 5 0 62 11)(font "Arial" ))
 	(pt 168 8)
 	(drawing
@@ -97,12 +101,13 @@ applicable agreement for further details.
 		(line (pt 109 4)(pt 113 8))
 		(line (pt 109 12)(pt 113 8))
 	)
-	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -16 200 48 216))
 )
 (pin
 	(input)
 	(rect 48 200 216 216)
-	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
 	(text "hot" (rect 5 0 21 11)(font "Arial" ))
 	(pt 168 8)
 	(drawing
@@ -113,12 +118,13 @@ applicable agreement for further details.
 		(line (pt 109 4)(pt 113 8))
 		(line (pt 109 12)(pt 113 8))
 	)
-	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -8 216 48 232))
 )
 (pin
 	(input)
 	(rect 32 216 216 232)
-	(text "INPUT" (rect 141 0 169 10)(font "Arial" (font_size 6)))
+	(text "INPUT" (rect 141 0 170 10)(font "Arial" (font_size 6)))
 	(text "sound_high_level" (rect 5 0 92 11)(font "Arial" ))
 	(pt 184 8)
 	(drawing
@@ -129,12 +135,13 @@ applicable agreement for further details.
 		(line (pt 125 4)(pt 129 8))
 		(line (pt 125 12)(pt 129 8))
 	)
-	(text "VCC" (rect 144 7 164 17)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 144 7 165 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -24 232 32 248))
 )
 (pin
 	(output)
 	(rect 648 136 824 152)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
 	(text "speed[1..0]" (rect 90 0 145 11)(font "Arial" ))
 	(pt 0 8)
 	(drawing
@@ -146,12 +153,13 @@ applicable agreement for further details.
 		(line (pt 82 8)(pt 78 12))
 		(line (pt 78 12)(pt 82 8))
 	)
+	(annotation_block (location)(rect 824 152 896 168))
 )
 (pin
 	(output)
 	(rect 648 152 824 168)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
-	(text "fan_auto" (rect 90 0 133 11)(font "Arial" ))
+	(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
+	(text "fan_auto" (rect 90 0 134 11)(font "Arial" ))
 	(pt 0 8)
 	(drawing
 		(line (pt 0 8)(pt 52 8))
@@ -162,12 +170,13 @@ applicable agreement for further details.
 		(line (pt 82 8)(pt 78 12))
 		(line (pt 78 12)(pt 82 8))
 	)
+	(annotation_block (location)(rect 824 168 888 184))
 )
 (pin
 	(output)
 	(rect 648 168 824 184)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
-	(text "alarm" (rect 90 0 118 11)(font "Arial" ))
+	(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
+	(text "alarm" (rect 90 0 119 11)(font "Arial" ))
 	(pt 0 8)
 	(drawing
 		(line (pt 0 8)(pt 52 8))
@@ -178,11 +187,12 @@ applicable agreement for further details.
 		(line (pt 82 8)(pt 78 12))
 		(line (pt 78 12)(pt 82 8))
 	)
+	(annotation_block (location)(rect 824 184 896 200))
 )
 (pin
 	(output)
-	(rect 648 184 824 200)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(rect 648 192 824 208)
+	(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
 	(text "hex7[6..0]" (rect 90 0 138 11)(font "Arial" ))
 	(pt 0 8)
 	(drawing
@@ -194,11 +204,12 @@ applicable agreement for further details.
 		(line (pt 82 8)(pt 78 12))
 		(line (pt 78 12)(pt 82 8))
 	)
+	(annotation_block (location)(rect 824 208 880 224))
 )
 (pin
 	(output)
-	(rect 648 200 824 216)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(rect 648 208 824 224)
+	(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
 	(text "hex6[6..0]" (rect 90 0 138 11)(font "Arial" ))
 	(pt 0 8)
 	(drawing
@@ -210,11 +221,12 @@ applicable agreement for further details.
 		(line (pt 82 8)(pt 78 12))
 		(line (pt 78 12)(pt 82 8))
 	)
+	(annotation_block (location)(rect 824 248 880 264))
 )
 (pin
 	(output)
-	(rect 648 216 824 232)
-	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(rect 648 248 824 264)
+	(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
 	(text "hex4[6..0]" (rect 90 0 138 11)(font "Arial" ))
 	(pt 0 8)
 	(drawing
@@ -226,79 +238,453 @@ applicable agreement for further details.
 		(line (pt 82 8)(pt 78 12))
 		(line (pt 78 12)(pt 82 8))
 	)
+	(annotation_block (location)(rect 824 264 880 280))
+)
+(pin
+	(output)
+	(rect 648 352 824 368)
+	(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
+	(text "fan" (rect 90 0 106 11)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 824 368 888 384))
+)
+(pin
+	(output)
+	(rect 648 368 824 384)
+	(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
+	(text "led_fan" (rect 90 0 127 11)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 824 384 888 400))
+)
+(pin
+	(output)
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