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author | Pacien TRAN-GIRARD | 2014-06-13 16:06:19 +0200 |
---|---|---|
committer | Pacien TRAN-GIRARD | 2014-06-13 16:06:19 +0200 |
commit | 70318492f3472ff2ec3b1735cf69a4eef1f6a51d (patch) | |
tree | 0f4243099ea9379bc164dc37a9fee3ab255f0f7e /FPGA/pwm/pwm.bdf | |
parent | d091bb2cb82f66d187df8f3aba6afcf4041b72ce (diff) | |
download | fpga-home-automation-70318492f3472ff2ec3b1735cf69a4eef1f6a51d.tar.gz |
Update project
Diffstat (limited to 'FPGA/pwm/pwm.bdf')
-rw-r--r-- | FPGA/pwm/pwm.bdf | 502 |
1 files changed, 502 insertions, 0 deletions
diff --git a/FPGA/pwm/pwm.bdf b/FPGA/pwm/pwm.bdf new file mode 100644 index 0000000..8e22468 --- /dev/null +++ b/FPGA/pwm/pwm.bdf | |||
@@ -0,0 +1,502 @@ | |||
1 | /* | ||
2 | WARNING: Do NOT edit the input and output ports in this file in a text | ||
3 | editor if you plan to continue editing the block that represents it in | ||
4 | the Block Editor! File corruption is VERY likely to occur. | ||
5 | */ | ||
6 | /* | ||
7 | Copyright (C) 1991-2013 Altera Corporation | ||
8 | Your use of Altera Corporation's design tools, logic functions | ||
9 | and other software and tools, and its AMPP partner logic | ||
10 | functions, and any output files from any of the foregoing | ||
11 | (including device programming or simulation files), and any | ||
12 | associated documentation or information are expressly subject | ||
13 | to the terms and conditions of the Altera Program License | ||
14 | Subscription Agreement, Altera MegaCore Function License | ||
15 | Agreement, or other applicable license agreement, including, | ||
16 | without limitation, that your use is for the sole purpose of | ||
17 | programming logic devices manufactured by Altera and sold by | ||
18 | Altera or its authorized distributors. Please refer to the | ||
19 | applicable agreement for further details. | ||
20 | */ | ||
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